The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a bi-polar transistor suitable for high speed operation and high density integration.
An example of a prior art concerning a semiconductor device including a bi-polar transistor is disclosed in Japanese patent application JP-A-59-80968. In a semiconductor device according to the disclosed prior art, a collector region is formed by a highly doped layer of n conductivity type buried in a substrate and an isolation between device elements such as transistors is made by the combination of a pn junction and a thick silicon oxide (hereinafter referred to as SiO.sub.2) film formed by means of selective oxidation.
FIG. 1 shows a cross-sectional structure of a bi-polar transistor included in the semiconductor device according to the above-mentioned art. In the figure, reference numeral 30 designates a silicon substrate of p.sup.- type, numeral 31 a buried collector layer of n.sup.+ type, numeral 32 a p.sup.+ for isolation between device elements, numeral 33 a region for isolation between device elements, numeral 34 an emitter, numeral 35 a base layer, and numeral 36 an SiO.sub.2 film. This bi-polar transistor is constructed in such a manner that the n.sup.+ buried collector layer 31, the base layer 35 and the emitter layer 34 are formed successively in that order on the p.sup.- substrate 30 and the inter-element isolation region 33 including the p.sup.+ isolation layer 32 and the SiO.sub.2 film 36 is provided between the adjacent device elements.
In general, a collector series resistance r.sub.CS of the bi-polar transistor is an important factor in implementing a device of high speed. Namely, when the collector series resistance r.sub.CS is high, it is difficult to operate the transistor at a high speed since the gain-bandwidth product f.sub.T is lowered and the transistor is liable to its saturated state in a large-current region. Therefore, it is necessary to maintain the collector series resistance r.sub.CS at a sufficiently low value. The collector series resistance r.sub.CB of the conventional bi-polar transistor shown in FIG. 1 is formed by a series resistance including a resistance r.sub.CS1 between a collector layer pulling region and the n.sup.+ buried collector region 31, a resistance r.sub.CS2 of the n.sup.+ buried collector layer 31, and a resistance r.sub.CS3 between the n.sup.+ buried collector layer 31 and a lightly doped collector layer of n.sup.- type, as is shown in the figure. A dominant resistance component which determines the magnitude of the collector series resistance r.sub.CS, is the resistance r.sub. CS2 or the resistance of the n.sup.+ buried collector layer 31. Usually, the sheet resistance of the n.sup.+ buried layer which is formed by doping with a donor type impurity such as Sb or As, has a magnitude on the order of 100 .OMEGA./.quadrature.. With reduction in the size of device elements such as transistors formed in a semiconductor device, it is required to further narrow the depth of the n.sup.+ buried collector layer in a direction of its thickness. Accordingly, the semiconductor device shown in FIG. 1 has a problem in that if high density is desired with respect to a structure, the collector series resistance r.sub.CS is effectively increased, thereby making high speed operation of the device difficult.
Also, in the above-mentioned conventional semiconductor device, if the width d of the isolation between the adjacent device elements formed by the combination of the SiO.sub.2 film 36 and the pn junction is designed to have a small value, the application of a negative bias to the collector layer results in a punch-through effect or may result in the depletion of the p.sup.+ isolation layer 32 provided in the inter-element isolation region 33, thereby rendering a conductive state between the adjacent buried collector layers of n.sup.+ and n.sup.+. Therefore, it is necessary to make the width d of the inter-element isolation region 33 larger than necessary, i.e., larger than a distance at which no punch-through of the p.sup.+ isolation layer 32 takes place. Accordingly, the conventional semiconductor device has the problem wherein the fine delineation of the inter-element isolation width is difficult to achieve and hence a high integration of the device cannot be achieved.
Further, the above-mentioned prior art has a further problem wherein a relatively large electrostatic capacitance is produced as a result of the pn junction between the p.sup.+ isolation layer 32 and the n.sup.+ buried collector layer 31 and this pn junction increases the electrostatic capacitance between the collector and the substrate, thereby making the operation speed of the semiconductor device slow.